· Daily Matrices · DAC Pavilion Panels · Business Day@DAC · Search the Program · Keynotes · Papers · Panels · Special Sessions · Monday Tutorial · Friday Tutorials · Intro to EDA · Interoperability · UML for SoC Design · Women's Workshop · Structured ASICs · Power Minimization	TUESDAY, June 8, 2004, 08:30 AM - 10:00 AM | Room: Ballroom 20ABC TRACK:BUSINESS    KEYNOTE    GigaScale Integration for Teraops Performance -- Challenges, Opportunities, and New Frontiers    Organizer(s): Sharad Malik      KEYNOTE SPEAKER: Pat Gelsinger, Chief Technology Officer , Senior Vice President, Intel Corp. VLSI system performance increased by five orders of magnitude in the last three decades, made possible by continued technology scaling, improving transistor performance to increase frequency, increasing integration capacity to realize complex architectures, and reducing energy consumed per logic operation to keep power dissipation within limit. The technology treadmill will continue, providing integration capacity of billions of transistors, enabling unprecedented tera-ops levels of performance; however, with some adverse effects posing barriers. Transistor subthreshold as well as gate leakage will impact supply voltage scaling, resulting in excessive power consumption. Therefore, transistor structure will have to change from today's basic bulk transistor to a complex structure of High-K dielectric, single or multiple gates per transistor, and polysilicon or a metal as a gate material. The interconnect performance will continue to get worse. Variations due to process, temperature, and supply voltage will have even more prominent effects, and tighter process control will limit design flexibility once taken for granted. Therefore, performance at any cost will not be an option; future system architectures will have to maximize performance in a given power envelope, and evolve innovative architectures to cope with increasing interconnect parasitics. Variations and tighter process control will have a major impact on the design methodology, making a bold move from today's deterministic design to statistical & probabilistic design. Future design automation tools must comprehend these paradigm shifts, be ready with design technology that comprehends new transistor structures, adopt statistical design methodology to overcome variations, comprehend tighter process controls, and still provide unprecedented productivity boost with gigascale integration. Pat Gelsinger is Senior Vice President and Chief Technology Officer of Intel Corporation. Gelsinger joined Intel in 1979, and has more than 20 years of experience in general management and product development positions. Gelsinger leads Intel's Corporate Technology Group, which encompasses many Intel research activities, including leading Intel Labs and Intel Research, and driving industry alignment with these technologies and initiatives. As CTO, he coordinates Intel's longer-term research efforts and helps ensure consistency from Intel's emerging computing, networking and communications products and technologies. Before his appointment as the company's first CTO, Gelsinger was the Chief Technology Officer of the Intel Architecture Group. In this position, he led the organization that researches, develops and designs next-generation hardware and software technologies for all Intel Architecture platforms for business and consumer market segments. Previously, Gelsinger led the Desktop Products Group, where he was responsible for Intel's desktop processors, chipsets and motherboards for consumer and commercial OEM customers as well as Intel's desktop technology initiatives and the Intel Developer Forum. From 1992 to 1996, Gelsinger was instrumental in defining and delivering the Intel(r) ProShare(r) video conferencing and Internet communications product line. Prior to 1992, he was general manager of the division responsible for the Pentium(r) Pro, IntelDX2(tm) and Intel486(tm) microprocessor families. Other positions Gelsinger has held during his Intel career include director of the Platform Architecture Group, design manager and chief architect of the original i486(tm) microprocessor, manager of CAD methodologies, and key contributor on the original i386(tm) and i286 chip design teams. Gelsinger holds six patents and six applications in the areas of VLSI design, computer architecture and communications. He has more than 20 publications in these technical fields, including "Programming the 80386," published in 1987 by Sybex Inc. He has received numerous Intel and industry recognition awards, and his promotion to group vice president at age 32 made him the youngest vice president in the history of the company. Gelsinger received an associate's degree from Lincoln Technical Institute in 1979, a bachelor's degree from Santa Clara University in 1983, Magna Cum Laude, and a master's degree from Stanford University in 1985. All degrees are in electrical engineering. Gelsinger is married and the father of four children.    Speaker(s): Pat Gelsinger - Intel Corp., Santa Clara, CA